(untitled) (Revista de Investigaciones Universidad del Quindío, 2009)
In this paper, architecture for co-design of signal processing applications from a model based on Simulink-Matlab is presented. This architecture is composed by a fixed-point Digital Signal Processor (DSP) and a Field Programmable Gate Array (FPGA). A parser translates the model specified on Simulink into C language routines or VHDL entities, which are compiled and downloaded to the DSP and the FPGA, respectively. Also, a kernel inside the DSP is responsible for task scheduling and communication of the hardware/software entities. The model of this system and the design of its kernel, hardware and parser are described.